Embodiments of the present invention relate to a production method. Further embodiments of the present invention relate to a method of producing tilted glass windows for wafer level encapsulation of microsystems. Further embodiments of the present invention relate to a method of producing a package for encapsulating a microscanner mirror.
There are many reasons why microsystem chips may be packaged. The most evident one is to protect the microsystem chips against the environment. [K. Najafi, “Micropackaging Technologies for Integrated Microsystems: Applications to MEMS and MOEMS”, Micromachining and Microproduction Process Technology VIII, Proceedings of SPIE 4979, 0 (2003)]. “Protection”, however, here does not necessarily means “total isolation” of the microsystem chip from the surroundings. Normally, microsystem chips communicate with the environment by means of electrical, optical or acoustic signals. When a microsystem chip involves optical communication with the environment, the most intuitive solution is to integrate a window transparent to the wavelength range that may be used for said optical communication into the package of the microsystem chip, as is shown in FIG. 1a. 
FIG. 1a shows a schematic view of a package 10 comprising a window 12 for encapsulating an MSD chip having a microscanner mirror 14 (MSD=microscanner devices). An incident light beam 16 impinges upon the surface of the microscanner mirror 14 and is reflected, as a reflected light beam 18, into a predefined region as a function of the deflection of the microscanner mirror 14. However, on the top side and bottom side of the window 12, parasitic reflections 20 of the incident light beam 16 arise which are reflected into the same region as the light beam 18 reflected by the microscanner mirror 14, which impairs the quality of the image generated by the microscanner mirror 14.
Such MSD chips are known, for example, from [H. Schenk, “The high versatility of silicon based micro-optical modulators”, MOEMS and Miniaturized Systems VII, ed. D. L. Dickensheets, H. Schenk, Proc. of SPIE 7208, 720802 (2009)].
A further problem may be the Fabry-Perot effect in MOEMS mirrors vibrating in parallel with the cap, as are applied in FTIR systems, for example. Here, too, this disturbing effect may be reduced or eliminated by tilting the window.
It is no trivial task to integrate a window 12 into the package 10 of a microsystem chip. It is even more demanding to hermetically seal the package [G. A. Riley, “Wafer-level Hermetic Cavity Packaging”, Advanced Packaging Magazine 13(5), 21 (2004)] and to arrange the window 12 such that it is tilted relative to the microscanner mirror 14, as is shown in FIG. 1 b. 
In addition, MSD chips entail vacuum-encapsulation so as to minimize, on the one hand, the energy consumption of the oscillating microscanner mirror and to increase, on the other hand, the resolution of the projection system [Hofmann et. al., “Wafer-level vacuum packaged micro-scanning mirrors for compact laser projection displays”, MOEMS and Miniaturized Systems VII, ed. D. L. Dickensheets, H. Schenk, Proc. of SPIE 6887, 688706 (2008)]. In addition, a tilted window 12 may be used for avoiding image distortions due to parasitic reflections 20 at the surfaces of the window 12. The parasitic reflections are caused by the difference in the refractive index between the material of the window 12 (e.g. glass) and the air. In a window 12 that is parallel to the device (e.g. the microscanner mirror), the parasitic reflections are reflected into the same region as the projected light, or image, 18, as is shown in FIG. 1a. This results in a parasitic dot or spot which permanently disturbs or impairs the projected image 18, which is unacceptable in particular for high-quality projection systems.
There are various approaches to liberating the projected image 18 from the parasitic reflections 20. For example, a Bragg reflector may be used which is deposited onto the surface (e.g. top side) of the window 12 in the form of a suitable layer stack. However, in this manner, only a small wavelength range may be suppressed, which is why this solution is not suitable for projecting colored images.
As was already mentioned above, another possibility is to tilt the window 12 at a suitable angle in relation to the device. As is shown in FIG. 1 b, the parasitic reflections 20 are thus no longer located within the projection range, which means that the projected image is no longer disturbed. The same effect can be achieved when instead of the window 12, the device is tilted relative to the window 12. Both cases in practice result in the problem of implementation, in particular when considering that the package should be vacuum-tight and low in cost.
An efficient possibility of realizing a low-cost vacuum package is WLP (wafer level packaging), as is shown in FIG. 2. It involves simultaneously packaging the chips on an, e.g., 6 or 8 inch wafer by means of a bonding method between a device wafer 22, which comprises the microsystem chips, and one or more cap wafer(s) 12 and 24 [M A. Schmidt, “Wafer-to-Wafer Bonding for Microstructure Formation”, Proceedings of the IEEE 86(8), 1575 (1998)] [V. Dragoi, “Wafer Bonding: Key Enabling Technology for Photonic Integration”, http://www.ieee.org/organizations/pubs/newsletters/leos/dec09/RH-Wafer Bonding.html (2009)]. Of course, one of the cap wafers 12 or 24, e.g. the upper cap wafer 12, should comprise an array of tilted windows 12 for packaging MSD chips.
In order to practically implement the structure shown in FIG. 2, the features mentioned in the following may be used. A device wafer comprising the MSD chips 22, a top cap wafer comprising the tilted windows 12, a bottom cap wafer, e.g. a raw silicon wafer 24, and a suitable bonding method for bonding the wafers 26. FIG. 2 shows an example of a vacuum-packaged chip with a window (e.g. made of glass) for interaction with the environment.
For bonding glass and silicon, or silicon and silicon, there are several well-established methods such as anodic bonding, eutectic bonding, and direct bonding, for example. The main problem in producing the structure shown in FIG. 2 therefore is not constituted by bonding the wafers, but by producing a top-cap wafer that is high-quality in terms of optics, is mechanically stable and comprises an array of tilted windows 12.
The challenges in producing top-cap wafers with tilted windows may thus be summarized as follows. Firstly, the tilted windows 12 are produced at the wafer level (e.g. on a 6 or 8 inch wafer) in order to be able to use the WLP approach. Secondly, glass cannot be easily structured at the wafer level by means of standard techniques such as wet etching, dry etching, laser etching, or laser structuring. Thirdly, the glass wafers have a high optical quality following structuring, e.g. the roughness of the structured windows, i.e. the peak-to-valley distance, should be smaller than λ/10 so as to allow the device to communicate with the environment without any disturbance or distortion. Fourthly, since glass is very brittle or fragile and since bonding involves applying pressure between the bonding partners, the finally structured wafer with the tilted windows should not crack during the bonding process. In fifth place, the glass used should have a linear coefficient of thermal expansion that is comparable with silicon so as to avoid cracking of the glass during the bonding process. Suitable glasses are Pyrex® or Borofloat®.
Typical wafer level microproduction technologies for silicon are photolithography and etching. As etching techniques, wet etching and dry etching are normally used. As compared to silicon, glass comprises no crystallographic features, so that structuring by means of wet etching, for example by means of buffered hydrofluoric acid (HF), results in microstructures having curved side walls and low aspect ratios. Dry etching, e.g. deep reactive ion etching, can be used to obtain microstructures having straight side walls; however, the depth of the microstructures is limited by the slow etch rate.
Another structuring technology used for structuring glass is laser structuring. However, due to poor thermal properties of most glasses, this structuring method may lead to cracks in the glasses or to other problems such as poor surface qualities of the glasses, for example. In addition, laser structuring cannot be used for large-area structuring of, e.g., 6 or 8 inch wafers.
Due to the limitations of the above-mentioned structuring technique, classical glass molding or glass blowing currently seems to be the most effective technique for structuring glass.
There are several documents, such as WO 2004/068665, U.S. Pat. No. 6,146,917, and US 2005/0184304, for example, which describe methods of producing optical windows for wafer level packaging of microsystem chips. However, in the cases mentioned, the windows are parallel to the device wafers. Consequently, said production methods are not applicable to the above-described MSD chip.
Methods for producing arrays of tilted or shaped windows are described in WO 2009/112138 A2, US 2008/0280124 A1, WO 2007/069165, US 2006/0176539 A1, and US 2007/0024549 A1.
For example, in WO 2009/112138 A2, a glass structuring process for wafer level packaging is described, where a glass wafer comprising so-called dummy support elements is bonded to a silicon wafer comprising cavities. During an annealing step at a temperature of more than 820° C., the glass softens, and the dummy support elements are pressed into the cavities in a controlled manner and thus form the glass as desired.
US 2008/0280124 A1 describes a glass blowing process at the wafer level [E. J Eklund and A. M. Shkel, “Glass Blowing on a Wafer Level”, J. of Microelectromechanical Systems 16(2), 232 (2007)]. The process is based on wafer bonding of a glass wafer and a structured silicon wafer under atmospheric pressure. The structured silicon wafer contains an array of cylindrical cavities comprising an increased volume in the bulk of the substrate, so that during the bonding process, a significant amount of gas can be stored inside the cavities. Subsequently, the bonded structure is subjected to an annealing step at a temperature of more than 820° C. During the annealing step, the gas stored within the silicon cavities will expand, the annealing temperature being above the softening point of the glass used, so that an array of spherical glass cavities will form. Said array of spherical glass cavities at the wafer level can be used be used for wafer level packaging of MSD chips so as to eliminate the parasitic reflections from the projection field. However, due to the mechanical forces applied during the bonding process or WLP process, the spherical cavities may be destroyed since in this case there is no more planar surface for applying force during bonding.